Learning To Program With Threads
Summary
The paper “Learning to Program with Threads” is a technical note written by A. Birrell in 1989 at the DEC SRC. It is a collection of “best practices” for using the concurrent programming capabilities of the SRC threading facilities. It is fairly lengthy, at 30 pages, but provides numerous exemplars for how to use the four basic components of multithreaded programs:
Creating threads
Synchronizing shared memory with mutexes
Condition variables
Alerts
Questions
The questions related to this paper fall into four basic categories:
What are the equivalent constructs in “X”?
Do the principles still hold today?
How does modern hardware affect performance?
Provide an example of how to use/avoid “X”.
All questions received are included as part of the slides at the end of the presentation.
Discussion
The discussion revolved mainly around two of the areas of questioning.
First, do the principles still hold? For the most part, modern thread systems look remarkably similar to the SRC system described in the paper. There has not been much change in the last 20 years. Some of the issues described in the paper such as priority inversion, which were presented without adequate solution do have standard methods in the POSIX thread library (mutex attributes) for mitigating the risks.
Concurrent programming is still difficult, and most of the (hard) work is still left to the programmer to sort out. Writing high performance multithreaded applications takes enormous skill. There is no magic bullet, or framework, the makes the job particularly easier than in the past. There are now tools, such as Intel’s VTune Thread Profiler which help find areas that are sapping performance.
The second main area of discussion was around modern hardware. Most new computer systems produced today have multiple cores. This means that the threads are truly simultaneous points of execution and that issues such as race conditions, deadlock, and corruption of unprotected shared memory are much more likely to occur. Cache coherency on multiple-core chips is an issue when writing multithreaded programs. Poor cache coherency, or thrashing of the cache can degrade performance significantly. The general feeling is that the hardware designers are currently leaving it up to the programmers to sort this out.
Questions related to “how does ‘x’ affect ‘y’” were largely postponed to later papers, as many of the concerns will be specifically dealt with by papers later in the course.